How can i download and install the gplcver (veriog tool) for 64-bit os in ubuntu?

Open a Terminal and run the following command to install gplcver

sudo apt-get update && sudo apt-get install gplcver

Or you can use Software Center to install gplcver

$ apt-cache show gplcver
Package: gplcver
Priority: extra
Section: universe/electronics
Installed-Size: 1776
Maintainer: Ubuntu Developers <email address hidden>
Original-Maintainer: NIIBE Yutaka <email address hidden>
Architecture: i386
Version: 2.12a-1.1
Depends: libc6 (>= 2.7)
Filename: pool/universe/g/gplcver/gplcver_2.12a-1.1_i386.deb
Size: 846096
MD5sum: e7be7e6007ade00cddb5845c2f131c1c
SHA1: 1e78951a6ea869e93e2d93d32e115f7150a0eeb3
SHA256: 1139abb05a6005b69eb82c7a703c346610d95a3a88c1d66caa384e72509c5dc2
Description-en: Verilog simulator
 Cver is a full 1995 IEEE P1364 standard Verilog simulator. It also
 implements some of the 2001 P1364 standard features. All three
 PLI interfaces (tf_, acc_, and vpi_) are implemented as defined
 in the IEEE 2001 P1364 LRM.
 .
 Homepage: http://www.pragmatic-c.com/gpl-cver
Description-md5: 5cd7e3e4b6737740e3284d654b0289b6
Bugs: https://bugs.launchpad.net/ubuntu/+filebug
Origin: Ubuntu

$

Hello Mark,

from ur code i install it... but when i run my code of verilog it show like this.it will not shows the variable name also space given.it show output but facing those problem.

I show this on my terminal when i compile my file "h.v"

Compiling source file "h.v"
Highest level modules:
test

                   0xxx
                  10010
                  20111
0 simulation events and 9 declarative immediate assigns processed.
7 behavioral statements executed (4 procedural suspends).
  Times (in sec.): Translate 0.0, load/optimize 0.1, simulation 0.1.
  There were 0 error(s), 0 warning(s), and 1 inform(s).
End of GPLCVER_2.12a at Sun Apr 1 10:29:29 2012 (elapsed 0.0 seconds).

My code in the h.v file is......
module andgate(c,a,b);

output c;
input a,b;
and h2(c,a,b);
endmodule

// test bench//

module test();

reg a,b;
wire c;
andgate h1(c,a,b);
// monitor the data//
initial
begin
$monitor($time," a=%b, b=%b ,c=%b",a,b,c);
end

///assign value///
initial
begin
#10;a=1'b0;b=1'b1;
#10;a=1'b1;b=1'b1;
end
endmodule

Hi,

I think I have answered your original question.

Could you please set this thread status to "solved" and create a new, separate question for your new issue?

Use this link:

https://answers.launchpad.net/ubuntu/+source/gplcver/+addquestion

Regards,

Mark